Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its stored data for some extended period without the application of power. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and removable memory modules, and the uses for non-volatile memory continue to expand.
Flash memory is typically arranged in a memory array 100 comprising a plurality of blocks of memory cells such as shown in FIG. 1, for example. Each row 102 of FIG. 1 represents a block of memory in a typical memory device. Data is stored in the memory array 100, i.e., an array of memory cells, by performing a programming operation on the memory device. Data can be read from the memory array 100 by performing a read operation.
Recognizing that errors might occur in the reading of data values from the memory device, the memory device might employ one or more types of error correction methods. Error Correction Schemes, commonly referred to as error correction codes (ECC), can be implemented in order to detect and/or attempt to correct these errors. Various ECCs comprise codes in which each data signal subjected to the ECC should conform to the specific rules of construction of the ECC. Departures from this construction of data (i.e., errors) that are not too great can generally be automatically detected and sometimes corrected. Examples of ECCs include Hamming code, BCH code, Reed-Solomon code, Reed-Muller code, Binary Golay code, Low-Density Parity code, and Trellis Code modulation. Some ECCs can correct single-bit errors and detect double-bit errors. Other ECCs can detect and/or correct multi-bit errors, for example.
Typically, a memory device will store user data in a first group of memory cells (which can be viewed as, for example, a first set of memory locations, a user data space, a user data portion and/or a user data storage area) and error correction code (ECC) data in a second group of memory cells of each block. These memory cell groupings are typically determined during design and layout of the memory device and the memory allocation for user data storage and ECC data storage is typically a permanent configuration of the memory device. During a read operation, both the stored user data and the ECC data are read from the memory array in response to a read request of the user data. Using known algorithms, the user data returned from the read operation is compared to the ECC data. If errors are detected and those errors are within the limits of the ECC, e.g., sufficient ECC resolution exists in the stored ECC data, the errors may be corrected.
By way of example, each block 102 of FIG. 1 is configured during design of the memory device based upon a desired ECC scheme to be utilized. Each user data memory area 110 has an associated ECC memory area 112. For example, ECC area 1121 stores ECC data associated with user data stored in user data storage area 1101, ECC area 1122 stores ECC data specific to user data stored in user data storage area 1102, etc. Block storage area 114 might store additional data (e.g., metadata) specific to the entire block 102, for example. This fixed configuration is repeated in each block of the memory device 100. Areas such as 112 and 114 are sometimes referred to collectively as overhead space.
However, different ECC codes require different amounts of memory cells to store their respective ECC data. Thus, if it is desired to accommodate more than one ECC code, the ECC data storage area of each block of the memory device is configured (e.g., allocated) to support an ECC code having the largest ECC storage requirements that might be utilized. However, this can be inefficient in situations wherein an ECC code is utilized which does not require the entire amount of allocated ECC data storage areas in the memory device, thus leaving memory cells unused and unavailable. A typical memory device might be allocated with blocks having 2048B (byte) of user data space and 140B of ECC data space to accommodate the largest ECC code(s) that might be desired. For example, ECC data storage areas 1121 and 1122 together might comprise 140B. This configuration (e.g., arrangement) of each block of memory would be repeated throughout the memory array 100. Thus, the memory array would comprise a number of blocks of memory each having the same user data space and ECC data space configuration per block. If an ECC is utilized which does not require the full 140B of ECC data space allocated for each block of user data cells, the remaining allocated ECC data space ends up not being utilized. Alternatively, if greater reliability is desired, the 140B of ECC data space might not be sufficient to store ECC data at the desired ECC resolution. For example, it may be desirable to have a particular level of reliability and a particular ECC code might be selected to be able to correct a certain number of errors occurring in user data stored in a memory device. If insufficient ECC data space is allocated, there might not be enough ECC data (e.g., insufficient ECC data resolution) to achieve the desired level of reliability and the number of errors that could be corrected might be reduced, for example.
As discussed above, the memory array configuration, such as shown in FIG. 1, is typically fixed and cannot be changed at a later time. However, some applications may require larger or smaller user data storage areas 110 than those originally allocated in the memory device. Thus, user data might not be as efficiently stored and/or retrieved from the memory device, for example. Further as part of the manufacturing process of the memory device, a controller in the memory device (e.g., control circuitry) is typically configured to interact with the memory array adhering to the fixed configuration of the blocks of memory cells, such as those shown in FIG. 1. For example, the memory array configuration data might be programmed into the controller utilizing firmware, for example. Thus, the controller may be permanently configured to operate with the memory array adhering to the memory device configuration programmed into the controller.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present disclosure, there is a need in the art for alternate configurations of memory cells in memory devices.